MC56F8037VLH

Product Summary

The MC56F8037VLH is a 16-bit Digital Signal Controller. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely costeffective solution.

Parametrics

MC56F8037VLH absolute maximum ratings: (1)Supply Voltage Range:-0.3V to 4.0V; (2)Analog Supply Voltage Range:- 0.3V to 4.0V; (3)ADC High Voltage Reference:- 0.3V to 4.0V; (4)Voltage difference VDD to VDDA:- 0.3V to 0.3V; (5)Voltage difference VSS to VSSA:- 0.3V to 0.3V; (6)Digital Input Voltage Range(Pin Groups 1, 2): - 0.3V to 6.0V; (7)Oscillator Voltage Range(Pin Group 4): - 0.4V to 4.0V; (8)Analog Input Voltage Range(Pin Group 3): - 0.3V to 4.0V; (9)Input clamp current, per pin (VIN < 0)1:-20.0 mA; (10)Output clamp current, per pin (VO < 0)1:-20.0 mA; (11)Output Voltage Range (Normal Push-Pull mode)(Pin Group 1): -0.3V to 4.0V; (12)Output Voltage Range (Open Drain mode)(Pin Group 2):-0.3V to6.0V; (13)Output Voltage Range (DAC)(Pin Group 5): - 0.3V to 4.0V; (14)Ambient Temperature Industrial:- 40℃ to 105℃; (15)Storage Temperature Range (Extended Industrial):-55℃ to 150℃.

Features

MC56F8037VLH features: (1)Efficient 16-bit 56800E family Digital Signal Controller (DSC)engine with dual Harvard architecture; (2)As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency; (3)Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC); (4)Four 36-bit accumulators, including extension bits; (5)32-bit arithmetic and logic multi-bit shifter; (6)Parallel instruction set with unique DSP addressing modes; (7)Hardware DO and REP loops; (8)Three internal address buses; (9)Four internal data buses; (10)Instruction set supports both DSP and controller functions; (11)Controller-style addressing modes and instructions for compact code; (12)Efficient C compiler and local variable support; (13)Software subroutine and interrupt stack with depth limited only by memory; (14)JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive,processor speed-independent, real-time debugging.

Diagrams